All MCQs

The page-table base register tells the address-translation hardware where the active page table begins.
It is changed during an address-space switch unless an alternative tagged scheme is used.

A page-table update may leave cached copies of the old translation on several CPUs.
The system sends coordination requests so those entries are invalidated consistently.

An address-space identifier tags cached translations with their owning process or address space.
This can avoid flushing the entire TLB on every context switch.

An inverted table reduces page-table memory by representing physical frames globally.
Entries typically include the owning process and virtual page information.

A hashed page table maps virtual page numbers into hash buckets containing translation entries.
It can represent sparse, very large virtual address spaces efficiently.

Multilevel page tables avoid allocating one enormous flat table for every possible virtual page.
Unused address-space ranges need no lower-level table.

Associative lookup searches by content rather than by a conventional numeric array index.
Parallel comparison allows rapid translation matching.

Most translations complete quickly when the TLB contains the requested entries.
Frequent misses require extra page-table accesses and increase average translation cost.

On a TLB hit, the processor obtains the frame number without an additional page-table memory access.
This lowers effective memory-access time.

A TLB stores recent virtual-page to physical-frame translations close to the processor.
It reduces the need to access the page table in main memory for every reference.

Reentrant read-only code can be safely mapped to the same physical frames for many processes.
Each process may still maintain private writable data pages.

Protection bits specify allowed operations such as read, write, or execute for a page.
The MMU checks these permissions during memory access.