Most translations complete quickly when the TLB contains the requested entries.
Frequent misses require extra page-table accesses and increase average translation cost.
Correct Answer: C. To allocate lower-level page-table portions only for used regions of a large address space
Explanation:
Multilevel page tables avoid allocating one enormous flat table for every possible virtual page.
Unused address-space ranges need no lower-level table.
A hashed page table maps virtual page numbers into hash buckets containing translation entries.
It can represent sparse, very large virtual address spaces efficiently.
Correct Answer: A. It has one entry for each physical frame rather than one entry for every virtual page
Explanation:
An inverted table reduces page-table memory by representing physical frames globally.
Entries typically include the owning process and virtual page information.
Correct Answer: B. To distinguish translations belonging to different processes
Explanation:
An address-space identifier tags cached translations with their owning process or address space.
This can avoid flushing the entire TLB on every context switch.
Correct Answer: C. Invalidating stale translations in other processors' TLBs after a mapping changes
Explanation:
A page-table update may leave cached copies of the old translation on several CPUs.
The system sends coordination requests so those entries are invalidated consistently.
Correct Answer: D. The referenced page is not part of the process's legal address space or is not currently valid for access
Explanation:
The valid-invalid mechanism lets hardware reject references outside the process's permitted pages.
In virtual-memory systems, related state can also indicate whether a legal page is resident.
Correct Answer: B. Multiple processes can map the same read-only code frames into their address spaces
Explanation:
Reentrant read-only code can be safely mapped to the same physical frames for many processes.
Each process may still maintain private writable data pages.